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NXP Semiconductors /QN908XC /DMA0 /INTENCLR0

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Interpret as INTENCLR0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLR

Description

Interrupt Enable Clear for all DMA channels.

Fields

CLR

Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data